Many functions of modern devices in automotive, consumer and industrial applications, such as computer technology, mobile communications technology, converting electrical energy and driving an electric motor or an electric machine, rely on field effect semiconductor transistors.
In order to improve the transistor switching speed and/or to reduce losses there are, in addition to further progresses in downscaling the transistor dimensions, ongoing developments to reduce parasitic device capacitances such as the Miller capacitance which is related to the gate-drain charge Qgd between the gate electrode and the drain region of the field effect transistor. The gate-drain charge Qgd is proportional to the overlap area and inversely proportional to the thickness of the gate dielectric along the gate electrode.
Several methods to reduce Qgd have been proposed, in particular for trench gate field effect transistors with insulated gate electrodes arranged in trenches. These methods include reducing the trench width, using a thicker dielectric along the trench bottom, eliminating portions of the gate along the trench flat bottom portion, extending the p-type well region of n-channel field effect transistors slightly deeper than the gate trench, and arranging an additional p-type region directly below the gate trench of n-channel field effect transistors. Each of these techniques has its own advantages and disadvantages. Some require a more complex process technology, while others are not so effective in reducing Qgd without adversely impacting other device characteristics. Furthermore, it is often required to minimize the Qgd variations related to varying processing conditions, for example to improve reliability and/or to minimize Miller capacitance variations of different gate electrodes of a power semiconductor device.